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Chrontel
CH7023/CH7024
Brief Datasheet
CH7023/CH7024 TV Encoder
Features
* * * * * TV encoder targeting handheld and similar systems Support for NTSC, PAL Video output support for CVBS or S-video MacrovisionTM 7.1.L1 copy protection support for SDTV (CH7023 only) Programmable 24-bit/18-bit/16-bit/15-bit/12-bit/8-bit digital input interface supporting various RGB and YCrCb (e.g. RGB565, RGB666, RGB888, ITU656 like YCrCb, etc.) input data formats Support for input resolutions up to 720x480 and 720x576 (e.g. 220x176, 320x240, 640x480, 720x480, 720x576, etc.) Adjustable brightness, contrast, hue and saturation. Detect TV / Monitor connection Two high quality10-bit video DAC outputs Fully programmable through serial port Flexible pixel clock frequency from graphics controller (2.3MHz--64MHz) Flexible input clock on the crystal or oscillator (2.3MHz--64MHz) Flexible up and down scaling on the display Master and slave mode Offered in 48-pin LQFP and 49-pin TFBGA Package IO voltage and SPC/SPD from 1.2V to 3.3V Programmable power management Power down current less than 20uA typical Power consumption of <150mW for one CVBS output, single terminated and <350mW for two DAC outputs, double terminated.
General Description
The CH7023/CH7024 is a TV encoder device targeting handheld, portable video applications such as digital still cameras and similar portable embedded systems. The device is able to encode the video signals and generate synchronization signals for NTSC and PAL standards. Supported TV output formats are NTSC-M, NTSC-J, NTSC-433, PAL-B/D/G/A/I, PAL-M, PAL-N and PAL60. The device accepts different data formats including RGB and YCrCb (e.g. RGB565, RGB666, RGB888, ITU656 like YCrCb, etc.) via 24 bit/18 bit/15 bit /12 bit /8 bit multiplexed digital inputs. Most embedded controllers are supported. The I/O interface voltage between CH7023/CH7024 and digital video source controller can be selected by the I/O supply voltage (VDDIO). The I/O supply voltage range is from 1.2V to 3.3V. The digital input voltage will follow the I/O supply voltage. CH7023/CH7024 is offered in both 48-pin LQFP package (7 x 7 mm) and 49-pin TFBGA package (6 x 6 mm). CH7023/CH7024 48-pin LQFP package comes with fixed single serial port address while 49-pin TFBGA package provide two user selectable serial port addresses via AS pin pull up or pull down option. Refer to application note AN-98 for more information.
*
* * * * * * * * * * * * *
RESET* XIN/FIN,XO XCLK P-OUT Sync Generation H,V DE D[23:0]
24 2
PLL
Serial Port Control
SPC SPD AS
2
Data Demux
CSC
Line Memory Based Scaler
DAC 0
TV Signal Formatter
DAC 1
CVBS Y C ISET
Two 10-bit DAC's
Figure 1: CH7023/CH7024 Block Diagram
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CHRONTEL 1.0 PIN-OUT
CH7023/CH7024
There are two major differences between CH7023/CH7024 48-pin LQFP and 49-pin TFBGA in pin-out: the video DACs output and the serial port address option using AS pin. The CH7023/CH7024 48-pin LQFP comes with three video output pins, primary CVBS (pin 28), S-video Y (pin 27) and secondary CVBS or S-video C (pin 26). The CH7023/CH7024 49-pin TFBGA comes with two video outputs, primary CVBS or S-video Y (pin E5) and secondary CVBS or S-video C (pin F6). The CH7023/CH7024 48-pin LQFP package comes with fixed single serial port address (76h - 7 bit address) while the CH7023/CH7024 49-pin TFBGA package provides two user selectable serial port addresses via AS pin pull up or pull down option.
1.1 Package Diagram
1.1.1 The 48-pin LQFP Package Diagram
D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] D[16] D[17] D[18]
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 32
AGND XO XI/FIN AVDD AVDD_PLL AGND_PLL ISET AGND_DAC CVBS Y C/CVBS AVDD_DAC
Chrontel CH7023/CH7024
31 30 29 28 27 26 25
Figure 2: 48-LQFP Package (top view)
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CHRONTEL
1.1.2 The 49-pin TFBGA Package Diagram
CH7023/CH7024
1
2
3
4
5
6
7
A
D8
D7
D5
D2
XCLK
VDDI O
P-OUT
B
D10
D9
D6
D1
H
XO
AGN D
C
D12
D11
D3
D0
XI
AVDD _PLL
AVDD
D
D15
D13
D4
V
ISET
AGN D_PL L
AGN D_DA C
E
D18
D16
D17
D14
CVBS /Y
NC
AVDD _DAC
F
D19
D21
D22
D23
SPD
CVBS /C
AS
G
D20
VDD
GND
DE
SPC
RESE T*
NC
Figure 3: 49-Pin TFBGA Package (top view)
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CHRONTEL
1.2 Pin Description
1.2.1 The 48-pin LQFP Pin Description
CH7023/CH7024
The 48-pin LQFP Package does not have AS pin to select second serial port address option. Refer to application note AN-98 for device address byte (DAB) details. The serial port device address for the read and write operation is fixed at ECh and EDh respectively. It has internal switch to provide separate primary CVBS (pin 28) and S-video Y (pin27) outputs. Refer to section 2.3.2 Video DAC output and the Control Register 0Ah for the video DAC output control. Table 1: Pin Description (48-pin LQFP) Pin # 42-48, 1-15, 17,19 40 Type In Symbol D[0]-D[23] Description Data[0] through Data[23] Inputs These pins accept 24 data input lines from a digital video port of a graphics controller. The swing is defined by VDDIO. Horizontal Sync Input / Output When the SYO control bit is low, this pin accepts a horizontal sync input for use with the input data. The amplitude will be 0 to VDDIO. When the SYO control bit is high, the device will output a horizontal sync pulse. The amplitude will be 0 to VDDIO. 39 In/Out V Vertical Sync Input / Output When the SYO control bit is low, this pin accepts a vertical sync input for use with the input data. The amplitude will be 0 to VDDIO. When the SYO control bit is high, the device will output a vertical sync pulse. The amplitude will be 0 to VDDIO. 20 In DE Data Enable When the pin is high, the input data is active. When the pin is low, the input data is blanking. - Reset * Input This pin is internally pulled high. When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port. Serial Port Data Input / Output This pin functions as the bi-directional data pin of the serial port and operates with input level from 0 to VDDIO. Outputs are driven from 0 to VDDIO. Serial Port Clock Input This pin functions as the clock pin of the serial port and operates with input level from 0 to VDDIO. Composite Video This is a primary composite vide output when S-video Y (pin 27) is not used. This output is turned off when S-video Y output is used. Luma Output The output is S-video luminance when the primary CVBS output (pin 28) is not used.
In/Out
H
24 23
- In
NC RESET*
21
In/Out
SPD
22
In
SPC
28
Out
CVBS
27
Out
Y
4
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CHRONTEL
Table 1: Pin Description (cont'd) Pin # 26 Type Out Symbol C/CVBS
CH7023/CH7024
Description Chroma/CVBS Output The output is S-video chrominance when S-video is used. But, when dual CVBS outputs are needed, this out pin can be used for secondary CVBS output in addition to the primary CVBS output (pin 28). Current Set Resistor This pin sets the DAC current. A 1.2k ohm, 1% tolerance resistor should be connected between this pin and AGND_DAC (pin 29) using short and wide traces. Pixel Clock Output This pin provides a clock signal to the graphics controller, which can be used as a reference frequency. The output driver is driven from the VDDIO supply. This output has a programmable tri-state. The capacitive loading on this pin should be kept to a minimum. Crystal Input / External Reference Input For master mode and some situation of the slave mode, a parallel resonance crystal (20 ppm) should be attached between this pin and XO. However, an external 3.3V CMOS compatible clock can drive the XI/FIN input. Crystal Output For master mode and some situation of the slave mode, a parallel resonance crystal (20 ppm) should be attached between this pin and XI/FIN. However, if an external CMOS clock is attached to XI/FIN, XO should be left open. External Clock Inputs The input is the clock signal input to the device for use with the H, V, DE and D[23:0] data. IO Supply Voltage (1.2-3.3V) Digital Supply Voltage (1.8V) Digital Ground
30
In
ISET
37
Out
P-Out
34
In
XI/FIN
35
Out
XO
41
In
XCLK
38 16 18 25 29 32 31 33 36
Power Power Power Power Power Power Power Power Power
VDDIO DVDD DGND
AVDD_DAC DAC Supply Voltage (2.5-3.3V) AGND_DAC DAC Ground AVDD_PLL AGND_PLL AVDD AGND PLL Supply Voltage (1.8V) PLL Ground Crystal Supply Voltage (2.5-3.3V) Crystal Ground
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1.2.2 The 49-pin TFBGA Pin Description
CH7023/CH7024
The 49-pin TFBGA Package has AS pin to select second serial port address. Refer to application note AN-98 for device address byte (DAB). The device address for read operation can be either ECh or EAh based on external pull-down or pull-up with AS pin respectively. The device address for write operation can be either EDh or EBh. It does not has internal switch to provide separate primary CVBS and S-video Y outputs. Instead, it has single or dual CVBSs or S-video C and Y output. Refer to section 2.3.2 Video DAC output and the Control Register 0Ah for the video DAC output control. Table 2: Pin Description (49-pin TFBGA) BGA Pin # A1-4,B1-B4,C1C4,D1-D3,E1-E4, F1-F4,G1 B5 Type In Symbol D[0]-D[23] Description Data[0] through Data[23] Inputs These pins accept 24 data input lines from a digital video port of a graphics controller. The swing is defined by VDDIO. Horizontal Sync Input / Output When the SYO control bit is low, this pin accepts a horizontal sync input for use with the input data. The amplitude will be 0 to VDDIO. When the SYO control bit is high, the device will output a horizontal sync pulse. The output is driven from the VDDIO supply. Vertical Sync Input / Output When the SYO control bit is low, this pin accepts a vertical sync input for use with the input data. The amplitude will be 0 to VDDIO. When the SYO control bit is high, the device will output a vertical sync pulse. The output is driven from the VDDIO supply. Data Enable When the pin is high, the input data is active. When the pin is low, the input data is blanking. Serial Port Address Select This pin is internally pulled low. When AS is high, the address is 75h - 7 bit address. Otherwise, the address is 76h - 7 bit address. - Reset * Input This pin is internally pulled high. When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the serial port. Serial Port Data Input / Output This pin functions as the bi-directional data pin of the serial port and operates with input level from 0 to VDDIO. Outputs are driven from 0 to VDDIO. Serial Port Clock Input This pin functions as the clock pin of the serial port and operates with input level from 0 to VDDIO. - Luma Output The output can be either a primary CVBS or S-video luminance. 209-0000-062 Rev. 1.14, 6/8/2007
In/Out
H
D4
In/Out
V
G4
In
DE
F7
In
AS
G7 G6
- In
NC RESET*
F5
In/Out
SPD
G5
In
SPC
E6 E5
- Out
NC CVBS/Y
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CHRONTEL
Table 2: Pin Description (cont'd) BGA Pin # F6 Type Out Symbol CVBS/C
CH7023/CH7024
Description Chroma Output The output can be either secondary CVBS when dual CVBSs are needed or S-video chrominance when S-video is selected. In single CVBS output mode, this output is turned off to save power. ISET Current Set Resistor This pin sets the DAC current. A 1.2k ohm, 1% tolerance resistor should be connected between this pin and AGND_DAC (pin D7) using short and wide traces. P-Out Pixel Clock Output This pin provides a clock signal to the graphics controller, which can be used as a reference frequency. The output driver is driven from the VDDIO supply. This output has a programmable tri-state. The capacitive loading on this pin should be kept to a minimum. XI/FIN Crystal Input / External Reference Input For master mode and some situation of the slave mode, a parallel resonance crystal (20 ppm) should be attached between this pin and XO. However, an external +3.3V CMOS compatible clock can drive the XI/FIN input. XO Crystal Output For master mode and some situation of the slave mode, a parallel resonance crystal (20 ppm) should be attached between this pin and XI/FIN. However, if an external CMOS clock is attached to XI/FIN, XO should be left open. XCLK External Clock Inputs The input is the clock signal input to the device for use with the H, V, DE and D[23:0] data. VDDIO IO Supply Voltage (1.2-3.3V) VDD Digital Supply Voltage (1.8V) GND Digital Ground AVDD_DAC DAC Supply Voltage (2.5-3.3V) AGND_DAC DAC Ground AVDD_PLL PLL Supply Voltage (1.8V) AGND_PLL PLL Ground AVDD Crystal Supply Voltage (2.5-3.3V) AGND Crystal Ground
D5
Out
A7
Out
C5
In
B6
Out
A5
In
A6 G2 G3 E7 D7 C6 D6 C7 B7
Power Power Power Power Power Power Power Power Power
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CHRONTEL 2.0 PACKAGE DIMENSIONS
CH7023/CH7024
Figure 4: 48 Pin LQFP Package
Table of Dimensions
No. of Leads 48 (7 X 7 mm) MilliMIN meters MAX A 9 B 7 C 0.5 D 0.17 0.27 SYMBOL E F 1.35 0.05 1.45 0.15 G 1.00 H 0.45 0.75 I 0.09 0.20 J 0 7
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CH7023/CH7024
Figure 5: 49 Pin TFBGA Package
Table of Dimensions
No. of Leads 49 (6 X 6 mm) MilliMIN meters MAX A 6.00 B 6.00 C 4.80 D 0.80 SYMBOL E F 4.80 0.80 G 1.20 H 0.22 0.32 I 0.26 J 0.53
Notes: 1. All dimensions conform to JEDEC standard MO-216.
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Disclaimer
CH7023/CH7024
This document provides technical information for the user. Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use of our products and assume no liability for errors contained in this document. The customer should make sure that they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number CH7023B-GF CH7023B-GF-TR CH7023B-DF CH7023B-DF-TR CH7024B-GF CH7024B-GF-TR CH7024B-DF CH7024B-DF-TR Package Type 49TFBGA, Lead-free 49TFBGA, Lead-free, Tape & reel 48LQFP, Lead-free 48LQFP, Lead-free, Tape & reel 49TFBGA, Lead-free 49TFBGA, Lead-free, Tape & reel 48LQFP, Lead-free 48LQFP, Lead-free, Tape & reel Copy Protection MacrovisionTM MacrovisionTM MacrovisionTM MacrovisionTM None None None None Output Video Switch No No Yes Yes No No Yes Yes Shipping Format Tray, 4290 per dry pack bag T&R, 2000 per dry pack bag Tray, 2500 per dry pack bag T&R, 1000 per dry pack bag Tray, 4290 per dry pack bag T&R, 2000 per dry pack bag Tray, 2500 per dry pack bag T&R, 1000 per dry pack bag
Chrontel
2210 O'Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com
(c)2007 Chrontel, Inc. All Rights Reserved. Printed in the U.S.A.
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209-0000-062
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6/8/2007

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